The present invention relates generally to cache management, and more particularly to maintaining cache coherence in a multiprocessor system.
Advances in semiconductor fabrication technology have given rise to considerable increases in microprocessor clock speeds. Although the same advances have also resulted in improvements in memory density and access times, there remains a disparity between microprocessor clock speeds and memory access times. To reduce latency, often one or more levels of high-speed cache memory are used to hold a subset of the data or instructions that are stored in the main memory. A number of techniques have been developed to increase the likelihood that the data/instructions held in the cache are repeatedly used by the microprocessor.
To improve performance at any given operating frequency, microprocessors with multiple cores that execute instructions in parallel have been developed. The cores may be integrated within the same semiconductor die, or may be formed on different semiconductor dies coupled to one another within a package, or a combination of the two. Each core may include its own level 1 cache which can store program data as well as instruction data (alternatively referred to as “instructions”) and an optional level 2 cache.